 | cpu16x1832@wmconnect.com wrote:
> Sunday, August 22nd, 2004
> 8:16am
>
> FORTH is an Object Oriented Language ( OOL)
>
....
ALL process control communications
via multi-cpu shared memory mapped RAM
(( use sixteen to simulate VLIW to/from shared RAM
thru two buses ( that may linkto type of 16*16)))
( sixteen-process-per-cpu *
sixteen-cpus-maximum-per-bus *
two-buses )
eight-bits ( with address and data) bus for
relative extended address
16processs/16cpus per bus maximum
( two-layer multi-plexer ,
one for cpu-bus ,
one for process-to-process link ) for
regular ( shared SMP) RAM is at the SMP level however,
Even with Intel Like DirectRamBus DRAM multiplexed RAM!
( the intel memory architecture maybe
( v.s. strict MPP SMP MPP , IBM like model , where VLIW
is simply a bus instruction to load memory /shadowed/ into
VLIW cache ( the first MPP )
THE VLIW RAM
( maybe some what like RAM of
an enhanced 25X (
Professor Charles H. Moore or Mr. Moore is O.K. with me)
as the first MPP of MPP SMP MPP where I use three stacks ( and keep
seperate
the return stack) for ram sharing parallel process
( again sixteen on a CPU16 or maybe like a 256X diaganale two-layer
multiplex bus, AGAIN stated as a possible description but not to be
taken too literally but try adding a C shared-bus++ ( FOR SHARED RAM)
and a 5-bit code is /switchable/ with X, Y ***OR*** the return stack,
EXIT ALWAYS USES THE REURN STACK. ( UMM)) I CURRENTLY DIVIDE THE
INSTRUCTION SET BY THE FIRT FOUR BITS, IF FIRST FOUR BITS ARE ZERO ,
THEN LOAD A VLIW ( INTO SMP(MPP)/MPP),
IF FIRST BIT IS ONE THEN EXECTUE 5-BIT PACKED CODE FOR 16-BIT
instructions,
literals and branches may cross 16-bit boundaries)
SMP(/MPP) MPP
PROVIDED AS IS WITHOUT ANY WARRANTY!
echo *
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